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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Universal Shift Register
High-Performance Silicon-Gate CMOS
The MC74HC195 is identical in pinout to the LS195. The device inputs are compatible with standard CMOS outputs, with pull up resistors, they are compatible with LSTTL outputs. This static shift register features parallel load, serial load (shift right), hold, and reset modes of operation. These modes are tabulated in the Function Table, and further explanation can be found in the Pin Description section. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 150 FETs or 37.5 Equivalent Gates LOGIC DIAGRAM
SERIAL DATA INPUTS J K A PARALLEL DATA INPUTS B C D CLOCK SERIAL SHIFT/ PARALLEL LOAD RESET 2 3 4 5 6 7 11 10 9 1 12 15 14
16
MC74HC195
N SUFFIX PLASTIC PACKAGE CASE 648-08
1
ORDERING INFORMATION MC74HCXXXN Plastic
PIN ASSIGNMENT
RESET J K A B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QA QB QC QD QD CLOCK SERIAL SHIFT/ PARALLEL LOAD
QA QB QC QD QD PARALLEL DATA OUTPUTS
C D GND
PIN 16 = VCC PIN 8 = GND
FUNCTION TABLE
Inputs Serial Reset L H H H H H H Shift/ Load X L H H H H H L Clock X J X X X L L H H K X X X H L H L A X a X X X X X Parallel B X b X X X X X C X c X X X X X D X d X X X X X QA0 L H QAn QA0 QAn QAn QAn QA L a QB L b Outputs QC L c No Change QBn QBn QBn QBn QCn QCn QCn QCn QCn QCn QCn QCn QD L d QD H d Operating Mode Reset Parallel Load Hold Retain First Stage Reset First Stage Set First Stage Toggle First Stage Serial Shift
H = high level (steady state) L = low level (steady state) X = don't care = transition from low to high level. a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively.
QA0 = the level of QA before the indicated steady-state input conditions were established. QAn, QBn, QCn = the level of QA, QB, or QC, respectively, before the most recent transition of the clock.
10/95
(c) Motorola, Inc. 1995
3-1
REV 6
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MAXIMUM RATINGS*
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC74HC195
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
VOL
ICC
TA
VIH
VIL
Iin
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP)
Storage Temperature
Power Dissipation in Still Air
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND Iout = 0 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Plastic DIP
v
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
3-2 - 65 to + 150 - 0.5 to + 7.0 - 55 Min 2.0 Value
v 4.0 mA v 5.2 mA
v 4.0 mA v 5.2 mA
0 0 0
0
50
25
20
260
750
+ 125
1000 500 400
VCC
Max
6.0
VCC V
6.0
6.0
4.5 6.0
2.0 4.5 6.0
4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.1
1.5 3.15 4.2
0.26 0.26
3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
0.3 0.9 1.2
8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 80
v
1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
160
v
Unit
A A V V V V
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tPLH, tPHL tPLH, tPHL tTLH, tTHL fmax Cin Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 5) Maximum Propagation Delay, Reset to any Q or QD (Figures 2 and 5) Maximum Propagation Delay, Clock to any Q or QD (Figures 1 and 5) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 5) Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C 150 30 26 145 29 25 6.0 30 35 10 75 15 13 Guaranteed Limit
High-Speed CMOS Logic Data DL129 -- Rev 6
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
CPD
trec
tr, tf
tsu
tsu
tw
tw
th
th
Power Dissipation Capacitance (Per Package)*
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Reset (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Recovery Time, Reset Inactive to Clock (Figure 2)
Minimum Hold Time, Clock to Serial Shift/Parallel Load (Figure 4)
Minimum Hold Time, Clock to A, B, C, D, J, or K (Figure 3)
Minimum Setup Time, Serial Shift/Parallel Load to Clock (Figure 4)
Minimum Setup Time, A, B, C, D, J, or K to Clock (Figure 3)
Parameter
3-3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C Typical @ 25C, VCC = 5.0 V 1000 500 400 100 20 17 100 20 17 80 16 14 80 16 14 5 5 5 3 3 3 3 3 3 Guaranteed Limit 1000 500 400 100 20 17 100 20 17 125 25 21 125 25 21 190 38 33 180 36 31 4.8 24 28 10 95 19 16 95 5 5 5 3 3 3 3 3 3 1000 500 400 120 24 20 120 24 20 150 30 26 150 30 26 225 45 38 220 44 38 110 22 19 4.0 20 24 10 5 5 5 3 3 3 3 3 3
v 85_C v 125_C
v 85_C v 125_C
MC74HC195
MOTOROLA MHz Unit Unit pF pF ns ns ns ns ns ns ns ns ns ns ns
MC74HC195
PIN DESCRIPTION
DATA INPUTS A, B, C, D (Pins 4, 5, 6, 7) Parallel data inputs. OUTPUTS QA, QB, QC, QD, QD (Pins 15, 14, 13, 12, 11) Parallel data outputs. CONTROL INPUTS Clock (Pin 10) Clock input. The shift register is completely static, allowing Clock rates down to DC in a continuous or intermittent mode. Serial Shift/Parallel Load (Pin 9) Shift or load control. A low level applied to this pin allows data to be loaded from the parallel inputs. Data is loaded with the positive transition of the Clock input. A high level allows data to be shifted in the manner dictated by the J and K control inputs. Reset (Pin 1) A low level applied to this pin resets all stages and forces all outputs low. J, K (Pins 2, 3) Shift Control. With Serial Shift/Parallel Load high, J and K control the mode of operation, as illustrated in the Function Table.
J = L, K = H With a positive transition of the Clock input, each bit is shifted to the right (in the direction QA toward QD) one stage and stage A maintains its previous state. J = H, K = L With a positive transition of the Clock input, each bit is shifted right (in the direction of QA toward QD) one stage and the QA output is inverted. J=K=L With a positive transition of the Clock input, each bit is shifted right (in the direction QA toward QD) one stage and a low is loaded into stage A. J=K=H With a positive transition of the Clock input, each bit is shifted right (in the direction QA toward QD) one stage and a high is loaded into stage A.
SWITCHING WAVEFORMS
tw RESET tr CLOCK 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL CLOCK tPHL Q 50% trec 50% VCC GND tf VCC GND tPLH Q 50% 50% GND tPHL VCC
Figure 1.
Figure 2.
VALID INPUT A, B, C, D, J, OR K VCC 50% GND tsu CLOCK th VCC 50% GND CLOCK SERIAL SHIFT PARALLEL LOAD 50%
VALID VCC GND tsu th VCC 50% GND
Figure 3.
Figure 4.
MOTOROLA
3-4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC195
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST
CL*
* Includes all probe and jig capacitance
Figure 5.
TIMING DIAGRAM
CLOCK RESET SERIAL DATA INPUTS SERIAL SHIFT/ PARALLEL LOAD PARALLEL DATA INPUTS J K A B C D PARALLEL DATA OUTPUTS QA QB QC QD SERIAL SHIFT RESET LOAD SERIAL SHIFT H L H L
High-Speed CMOS Logic Data DL129 -- Rev 6
3-5
MOTOROLA
EXPANDED LOGIC DIAGRAM
SERIAL DATA INPUTS K 3 VCC PARALLEL DATA INPUTS D 7 6 4 VCC C B 5 A J 2
MOTOROLA D D C C Q RR C C Q RR 10 D C C Q RR D C C Q RR VCC = PIN 16 GND = PIN 8 1 11 QD 12 QD 13 QC PARALLEL DATA OUTPUTS 14 QB 15 QA
MC74HC195
SERIAL SHIFT/ 9 PARALLEL LOAD
3-6
CLOCK
High-Speed CMOS Logic Data DL129 -- Rev 6
RESET
MC74HC195
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
B
1 8
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
3-7
*MC74HC195/D*
MC74HC195/D MOTOROLA

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